A portion of the disclosure of this patent document contains matter subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent disclosure document as it appears in the Patent and Trademark Office files and records but otherwise retains all copyrights whatsoever.
1. Field of the Invention
The present invention relates to multilayer printed circuit boards and, more particularly, to registration of multilayer printed circuit boards (MLB) prior to lamination.
2. Description of Related Art
There are few problems as challenging or as important in the printed circuit board industry as registration. Examination of the MLB scrap pile at drill or electrical testing sites can be mysterious and aggravating. One circuit out of a lot or on a panel may be perfect and the next circuit may be a confusing pattern of errors. If the scrap amount is significant, then there is need for immediate circuit board design modifications. Often the modifications required to correct the registration problems are not apparent so that the modifications that are implemented often give unsatisfactory results.
Multilayer printed circuit board registration errors come from a variety of sources including: (1) offset error; (2) angle error; (3) random noise; (4) compensation error. Compensation errors arise from mistakes in estimating the shrinking or expanding of the MLB due to material movement experienced following multilayer lamination of the cores and dielectric.
Unfortunately, in estimating the required compensation, the prior art merely suggests considering the amount of copper on an individual core by image, and the thickness of the core with no regard to the overall multilayer board design and construction. The data used to generate the matrix in the prior art is based on historical production information. These prior art models fail to precisely estimate the required compensation, and at times, produce as much as a xc2x115 mil error between the model and the actual production. One example of a prior art compensation matrix is shown in FIG. 1. The matrix is for 24xe2x80x3xc3x9718xe2x80x3 panels where the warp (X-direction) direction is 18xe2x80x3 and the fill (Y-direction) direction is 24xe2x80x3. The prior art matrix is based solely on the amount of copper on the core by image and the thickness of the core, dramatically limiting the usefulness in reducing compensation error.
In practice, use of the prior art compensation matrix disrupts the processing of multilayer printed circuit boards. FIG. 2 shows a flow chart of a simplified process map for a compensation process for a large printed circuit board shop. Arrows 30 in FIG. 2 indicate areas of the process that are very unstable. In a feedback process, which FIG. 2 describes, adding the wrong information will cause small mistakes that create large registration errors. This occurs when the feedback information is wrong or the feedback happens after a long lag period. Unfortunately, the nature of printed circuit board shops with large amounts of work in process greatly limits the ability to remove the detrimental lag time. Incomplete information and delay of input also limits the ability to make compensation changes on the fly. Making compensation changes after full production lots have been released is nothing more than process tampering, which often leads to escalating scrap rates. One way to improve compensation error is by improving the accuracy of compensation predictions for a job prior to production. Prior art strategies based on historical production data sets lack the required design combinations to detect the important variables and interactions that control the material movement. Therefore, the prior art compensation matrices do not accurately predict the error prior to production, thereby requiring costly modifications during production.
At block 32 of FIG. 2, the initial compensation values are selected from the sizing matrix of FIG. 1. At block 34, the test books (which typically 10 or more MLBs stacked on top of one another) and first production lots are xe2x80x9creleasedxe2x80x9d (started) to production. Due to time pressures, it is typically not feasible to first run tests to determine whether there will be production problems (i.e., whether the predicted compensation values were, in fact, correct) and then run the actual production. Instead, the test books and the production lots must be prepared for production simultaneously. At block 36, the test books are measured for errors and the production is run. Thereafter, at block 38, the overages (which are additional cores that have layers etched on them) are collected in the core inventory. Because some of the printed circuit boards are expected to fail, overages of additional cores with layers are manufactured. These overages are stored in the event that they are needed.
At block 40 of FIG. 2, based on the measurements of the test books in block 42, the artwork is changed in order to reduce compensation errors. However, due to old lots still being in the production pipeline, the old lots are still being used, as shown in block 44, which cause an unstable lag in terms of correcting the problems in the production. And, due to time pressures, the old cores are still used in the production, as shown at block 46.
The present methods of determining and correcting MLB registration errors are ineffective and unpredictable, resulting in large volumes of scrap. Thus, there remains a need to determine registration errors and in particular compensation error before production begins rather than during production.
In addition, the prior art fails to appreciate the interaction between the different sources of registration error. Typically, the prior art merely adds the variances which comprise the sources of registration error in an attempt to compute the total registration error. For example, compensation error from artwork, offset error and angle error from a post etch punch machine, and random noise from a drill machine cannot be combined by using the sum of the squares. However, this one-dimensional analysis does not provide insight on how the errors flow over the panel surface and how the sources of registration error are interdependent, combining to produce complex and seemingly unexplainable registration error patterns. There remains a need to account for the interaction of all types of errors in order to improve MLB registration.
In a first aspect of the invention, a method for modeling compensation during registration of a printed circuit board is provided. The method comprises the step of providing a plurality of printed circuit boards with multiple cores which use at least one dielectric layer in between the cores. The method also comprises the step of measuring the movement of least one core of each printed circuit board due to fabrication. And, the method comprises the step of generating a compensation model based on the core movement and based on the at least one dielectric layer.
In a second aspect of the invention, a method for modeling compensation during registration of a printed circuit board is provided. The method comprises the step of providing printed circuit boards with multiple cores with dielectric layers in between the cores, the cores having positions in the printed circuit boards. The method also comprises the step of measuring the movement of the cores due to fabrication of the printed circuit boards. And, the method comprises the step of generating a compensation model based on the core movement and based on the position of the cores in the printed circuit board.
In a third aspect of the invention, a method for modeling compensation during registration of a printed circuit board is provided. The method comprises the step of providing printed circuit boards having at least a first core and a second core, with circuit layouts on at least one side of the first core and on at least one side of the second core. The method also comprises the step of measuring the cores of the printed circuit boards after fabrication in order to measure movement of each core. And, the method comprises the step of generating a compensation model based on the measuring of the cores of the printed circuit boards and based on the circuit layouts on at least one side of the first core and on at least one side of the second core.
In a fourth aspect of the invention, a method for reducing compensation error during processing of a multilayer printed circuit board having multiple cores, circuits on the cores and dielectric layers in between the circuits is provided. The method comprises the step of identifying at least one characteristic of the multilayer printed circuit board selected from the group consisting of position of the core in the multilayer printed circuit board, the dielectric layer, and circuits on adjacent cores. The method also comprises the step of generating at least one compensation factor based on the at least one characteristic from a compensation model. And, the method comprises the step of modifying the circuits based on the at least one compensation factor.
In a fifth aspect of the invention, a simulator for determining compensation error in a multilayer printed circuit board having at least one dielectric layer, multiple cores, circuit configurations on the multiple cores is provided. The simulator comprises a processor and a memory device electrically connected to the processor, the memory device including a matrix of compensation error data comprising X and Y error measurements based on at least one characteristic of the multilayer printed circuit board selected from the group consisting of the at least one dielectric layer, position of the core in the stack, the circuit configurations on the multiple cores, assembly of the multilayer printed circuit board, and interaction between the core and the dielectric layer.
In a sixth aspect of the invention, a method of simulating errors during registration of a printed circuit board is provided. The method comprises the step of compiling at least a plurality of points on a layer in the multilayer printed circuit board. The method also comprises the step of modifying the position of the plurality of points based on an offset model, an angle model, a compensation model and a random noise model in order to created a modified position of the plurality of points. And, the method comprises the step of outputting a comparison of the position of the plurality of points with the modified position of the plurality of points.
In a seventh aspect of the invention, a method of simulating errors during registration of a printed circuit board is provided. The method comprises the step of determining true positions necessary to achieve perfect registration. The method also comprises the step of identifying at least two sources of errors which occur during registration. The method further comprises the step of combining the at least two sources of errors which occur during registration in an interdependent manner. And, the method comprises the step of comparing the combining of the at least two sources of errors with the true positions.
It is an object of the present invention to provide a method and apparatus for properly estimating the required compensation after lamination of a printed circuit board.
It is a further object of the present invention to provide a method and apparatus for simulating the registration errors in order to better design the circuit panel layout and understand the required production process controls.